The invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a semiconductor device having a gate spacer layer with a uniform thickness.
Generally, performance of an enormous number of processes is required to fabricate a semiconductor memory device such as a dynamic random access memory (DRAM). These processes include a stacking process, an etching process, and an ion implantation process, which are typically performed by a wafer unit. However, these wafer unit processes are not uniformly performed on a wafer, since there may be limitations such as equipment uniformity for processes or uniformity of process conditions. For example, a loading effect occurs during a process of fabricating a semiconductor, so that uniformity of the process can be adversely affected. The loading effect may be shown in various manufacturing processes. For example, while performing an etching process on the same wafer, an etching rate difference or a profile difference occurs due to the loading effect, which is caused depending on the size of a wafer exposed to plasma.
The uniformity of the process may cause many restrictions in device performance. For example, an insulating layer for a gate spacer, e.g., a nitride layer, is deposited and then a conventional anisotropic etching process is performed on the nitride layer to form a gate spacer layer on a sidewall of a gate. At this point, the loading effect may occur during the nitride layer deposition process or the etching process. Therefore, the gate spacer layer with a uniform thickness may not be formed on an entire surface of the wafer. For example, the center of the wafer has a relatively small thickness of the gate spacer layer and its edge has a relatively large thicknesses of the gate spacer layer.
If the thickness of the gate spacer layer is not uniform, a threshold voltage of a p-type metal oxide semiconductor (PMOS), especially in a peripheral circuit region, can be affected, so that a uniform threshold voltage may not be realized over the entire surface of a wafer. That is, due to the thickness difference between the center and the edge of the wafer, threshold voltage distribution of a PMOS in a peripheral circuit region may differ from that of the remainder of the circuit. Particularly, relatively high threshold voltage distribution may occur at the center of the wafer where the thickness of a gate spacer layer is relatively thin. Also, relatively low threshold voltage distribution may occur at the edge of the wafer where the thickness of a gate spacer layer is relatively thick.